Question: What is the purpose of a logic synthesis tool in PLD design?

Options:

1. To convert high-level code into a gate-level representation
2. To simulate the behavior of the PLD
3. To program the PLD directly
4. To test the PLD after programming

Correct Answer: To convert high-level code into a gate-level representation

Solution:

A logic synthesis tool converts high-level code (like VHDL or Verilog) into a gate-level representation that can be implemented on a PLD.