Q. In a T Flip-Flop, what does the T input control?
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A.
The output state
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B.
The clock frequency
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C.
The reset condition
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D.
The data input
Solution
The T input in a T Flip-Flop controls whether the output state toggles or remains the same on each clock pulse.
Correct Answer:
A
— The output state
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Q. In an SR Flip-Flop, what condition is considered invalid?
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A.
S=0, R=0
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B.
S=1, R=0
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C.
S=0, R=1
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D.
S=1, R=1
Solution
The condition S=1 and R=1 is invalid for an SR Flip-Flop as it leads to an indeterminate state.
Correct Answer:
D
— S=1, R=1
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Q. In an SR flip-flop, what condition leads to an invalid state?
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A.
S=0, R=0
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B.
S=1, R=0
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C.
S=0, R=1
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D.
S=1, R=1
Solution
The condition S=1 and R=1 leads to an invalid state in an SR flip-flop, as it creates an ambiguous output.
Correct Answer:
D
— S=1, R=1
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Q. What is the characteristic table of a JK Flip-Flop when both J and K inputs are high?
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A.
No change
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B.
Set
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C.
Reset
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D.
Toggle
Solution
When both J and K inputs are high, the JK Flip-Flop toggles its output state.
Correct Answer:
D
— Toggle
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Q. What is the main advantage of using a D Flip-Flop over an SR Flip-Flop?
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A.
Simplicity
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B.
No invalid states
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C.
Higher speed
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D.
Lower power consumption
Solution
The D Flip-Flop eliminates the invalid state issue present in the SR Flip-Flop, making it more reliable for data storage.
Correct Answer:
B
— No invalid states
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Q. What is the main difference between SR and JK Flip-Flops?
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A.
JK Flip-Flop has no invalid state
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B.
SR Flip-Flop has a toggle feature
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C.
JK Flip-Flop is slower
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D.
SR Flip-Flop can only set or reset
Solution
The main difference is that the JK Flip-Flop does not have an invalid state when both inputs are high, unlike the SR Flip-Flop.
Correct Answer:
A
— JK Flip-Flop has no invalid state
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Q. What is the output of a D Flip-Flop when the D input is low and the clock signal transitions?
-
A.
High
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B.
Low
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C.
Toggle
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D.
Undefined
Solution
The output of a D Flip-Flop will be low when the D input is low at the time of the clock transition.
Correct Answer:
B
— Low
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Q. What is the output state of a D Flip-Flop when the D input is 0 at the clock edge?
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A.
1
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B.
0
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C.
Toggle
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D.
Indeterminate
Solution
The output of a D Flip-Flop will be 0 when the D input is 0 at the clock edge.
Correct Answer:
B
— 0
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Q. What is the output state of a D flip-flop when the D input is low at the clock edge?
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A.
High
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B.
Low
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C.
Toggle
-
D.
Undefined
Solution
The output state of a D flip-flop will be low when the D input is low at the clock edge.
Correct Answer:
B
— Low
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Q. What is the primary function of a flip-flop in digital circuits?
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A.
To amplify signals
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B.
To store binary data
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C.
To perform arithmetic operations
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D.
To convert analog signals to digital
Solution
A flip-flop is a bistable device that can store one bit of binary data, making it essential for memory storage in digital circuits.
Correct Answer:
B
— To store binary data
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Q. What is the primary use of flip-flops in digital systems?
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A.
Data transmission
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B.
Data storage
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C.
Signal amplification
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D.
Analog processing
Solution
Flip-flops are primarily used for data storage in digital systems, holding binary information.
Correct Answer:
B
— Data storage
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Q. What is the purpose of the clock input in flip-flops?
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A.
To reset the flip-flop
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B.
To synchronize data storage
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C.
To amplify the input signal
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D.
To control the output voltage
Solution
The clock input in flip-flops is used to synchronize data storage, ensuring that changes occur at specific times.
Correct Answer:
B
— To synchronize data storage
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Q. What is the purpose of the clock signal in flip-flops?
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A.
To reset the flip-flop
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B.
To synchronize data storage
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C.
To amplify the signal
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D.
To provide power
Solution
The clock signal is used to synchronize data storage in flip-flops, determining when the input data is captured.
Correct Answer:
B
— To synchronize data storage
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Q. Which flip-flop can be used to create a shift register?
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A.
D Flip-Flop
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B.
T Flip-Flop
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C.
JK Flip-Flop
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D.
SR Flip-Flop
Solution
D Flip-Flops are commonly used to create shift registers, as they can store and shift data serially.
Correct Answer:
A
— D Flip-Flop
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Q. Which flip-flop can be used to divide the frequency of a clock signal by 2?
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A.
D Flip-Flop
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B.
T Flip-Flop
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C.
JK Flip-Flop
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D.
SR Flip-Flop
Solution
The T Flip-Flop toggles its output on each clock pulse, effectively dividing the input frequency by 2.
Correct Answer:
B
— T Flip-Flop
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Q. Which flip-flop is commonly used for frequency division?
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A.
D Flip-Flop
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B.
T Flip-Flop
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C.
JK Flip-Flop
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D.
SR Flip-Flop
Solution
The T Flip-Flop is commonly used for frequency division because it toggles its output on each clock pulse.
Correct Answer:
B
— T Flip-Flop
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Q. Which flip-flop is known for its ability to set and reset based on two inputs?
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A.
D Flip-Flop
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B.
T Flip-Flop
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C.
JK Flip-Flop
-
D.
SR Flip-Flop
Solution
The SR Flip-Flop has two inputs, Set (S) and Reset (R), allowing it to control the output state directly.
Correct Answer:
D
— SR Flip-Flop
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Q. Which flip-flop is known for its ability to toggle based on a single input?
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A.
D Flip-Flop
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B.
T Flip-Flop
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C.
JK Flip-Flop
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D.
SR Flip-Flop
Solution
The T Flip-Flop is known for its ability to toggle its output state based on a single input signal.
Correct Answer:
B
— T Flip-Flop
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Q. Which type of flip-flop is triggered by the rising edge of the clock signal?
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A.
D Flip-Flop
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B.
T Flip-Flop
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C.
JK Flip-Flop
-
D.
SR Flip-Flop
Solution
The D Flip-Flop is designed to capture the value of the D input at the rising edge of the clock signal.
Correct Answer:
A
— D Flip-Flop
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